The present invention relates generally to the field of host processor to peripheral interfacing, and more particularly to a bus interface circuit for use in conjunction with a peripheral device having a clock that is not synchronized with the host processor clock.
Digital system applications that require a host processor to be interfaced with peripheral processing devices are prevalent. In such applications, the peripheral device is typically programmed to carry out input/output operations and/or data processing separately from the host processor. Consequently, such a peripheral device may contain its own processor, input/output circuitry, clock and control circuitry, and different addressable memory locations.
In such applications it is not always desirable to synchronize the peripheral clock with the clock in the host processor, so the peripheral clock can run at any speed relative to the host processor clock (either faster or slower). As a result of the difference between the peripheral and host processor clocks, as well as the architecture and particular type of memory units employed in the peripheral device, the access time for different addressable memory locations within the peripheral can vary.
For a host processor to access (i.e., write data to and read data from) memory locations within the above described general peripheral processing device, an interfacing circuit is required for coupling the host processor and peripheral address and data buses, and to provide the appropriate timing for data transfers.
Consequently, there exists a need for a generic bus interface circuit for interfacing a host processor with a processing peripheral device, where the host processor and peripheral can have different asynchronous clocks, and peripheral memory locations accessible to the processor can have different access times.
As digital systems evolve to the point where the host processor, memory and several peripheral subsystems are all co-located on the same semiconductor substrate, it is important to minimize power dissipation and to conserve gate count within the interconnect structure. Furthermore, it is desirable to have circuit modules, (referred to as core circuits, or cells) that can be designed once and the designs reused and interconnected in a number of different digital systems in different combinations.
An illustrative embodiment of the present invention seeks to provide a bus for interconnecting common peripherals operating asynchronously to a host processor in a gate-efficient, low power implementation that can support zero wait state bus transactions and that avoids or minimizes above-mentioned problems.
Aspects of the invention are specified in the claims. In carrying out principles of the present invention a method for transferring data on a data bus between a first device operating in accordance with a first clock signal and a second device operating in accordance with a second clock signal, comprises the steps of: starting a first data transfer between the first device and the second device by asserting a strobe signal on the data bus, the strobe signal having at least a first pulse, wherein the strobe signal is synchronized to the first clock signal; and completing the first data transfer by asserting a ready signal on the data bus synchronized with the strobe signal, such that a first variable number of wait states is induced in response to a first ready state of the second device, wherein each additional pulse on the strobe signal after the first pulse corresponds to a wait state.
According to another feature of the invention, a digital system having data bus for transferring data connected between a first device operating in accordance with a first clock signal and a second device operating in accordance with a second clock signal, comprises: strobe circuitry in the first device connected to the data bus for starting a first data transfer between the first device and the second device by asserting a strobe signal on the data bus, the strobe signal having at least a first pulse, wherein the strobe signal is synchronized to the first clock signal; wait state circuitry in the second device operating in synchronism with the second clock signal, the state circuitry operable to store a ready state; and ready circuitry in the second device connected to the data bus and to the wait state circuitry for completing the first data transfer by asserting a ready signal on the data bus synchronized with the strobe signal, such that a first variable number of wait states is induced in response to a first ready state of the second device, wherein each additional pulse on the strobe signal after the first pulse corresponds to a wait state.
According to another feature of the invention, there is no free running clock signal associated with the data bus; and the strobe circuitry stops asserting the strobe signal in response to the ready signal, whereby in a period between the first data transfer and the second data transfer, the data bus has no active signals.
According to another feature of the invention, a cell for an Application Specific Integrated Circuit (ASIC) design library for synchronizing between a data bus and a device, comprises: an input to receive a strobe signal from the data bus, the strobe signal having at least a first pulse, wherein the strobe signal is synchronized to a first clock signal; wait state circuitry operable to store a ready state, the wait state circuitry being synchronized a second clock signal; an output to provide a ready signal to the data bus, the ready signal connected to ready circuitry operable to assert the ready signal on the data bus synchronized with the strobe signal, such that a first variable number of wait states is induced in response to a first ready state, wherein each additional pulse on the strobe signal after the first pulse corresponds to a wait state; and synchronization circuitry connected to the ready circuitry, operable to synchronize each data transfer to/from the data bus with the second clock in background, such that a first number of wait states is zero.